1. Field of the Invention
The present invention relates to a synchronous serial data transfer device, to which a plurality of external receiving circuits are connected, for transferring data items serially to each of the plurality of external receiving circuits in synchronization with a clock signal, and, more particularly, to an interface of data input/output terminals or clock input/output terminals for connecting the synchronous serial data transfer device to the external receiving circuits after the final data item has been transferred.
2. Description of the Prior Art
FIG. 12 is a block diagram showing a conventional synchronous serial data communication system and FIG. 13 is a block diagram showing the internal configuration of a conventional synchronous data transfer device shown in FIG. 12. In FIGS. 12 and 13, the reference number 1 designates the conventional synchronous data transfer device for transferring data items serially in synchronization with a clock signal, 2a to 2n denote a plurality of external receiving circuits for receiving transfer data items transferred from the conventional synchronous data transfer device 1. The reference number 11 indicates a data output terminal through which data items are transferred from the conventional synchronous serial data transfer device 1 to the external receiving circuits 2a to 2n. The reference number 12 denotes a clock output terminal through which a clock signal is transferred from the conventional serial data transfer device 1 to the external receiving circuits 2a to 2n. The reference number 13 designates a data input terminal through which each of the external receiving circuits 2a to 2n receives data transferred through the data output terminal 11 of the conventional synchronous serial data transfer device 1. The reference number 14 indicates a clock input terminal through which each of the external receiving circuits 2a to 2n receives the clock signal provided from the synchronous serial data transfer device 1.
Further, the reference number 21 designates a clock signal generation means for generating the clock signal which will be transferred to the external receiving circuits 2a to 2n through the clock output terminal 12. The reference number 22 indicates a serial data output means for receiving input data items in parallel from external devices (not shown), then for converting the input data items to serial data items, and for transferring the converted serial data items as transfer data items to the external receiving circuits 2a to 2n through the data output terminal 11 in synchronization with the clock signal supplied by the clock signal generation means 21.
Next, the operation of the conventional synchronous serial data transfer device 1 will be explained.
When receiving input data items transferred from the external devices (not shown) in parallel, the synchronous serial data transfer device 1 converts these input data items into serial data items by using the serial data output means 22. Then, the synchronous serial data transfer device 1 generates transfer data items according to the converted serial data items in synchronization with the clock signal generated by the clock signal generation means 21. The synchronous serial data transfer device 1 transfers the transfer data items through the data output terminals and also transfers the clock signal through the clock output terminal 12 to the external receiving circuits 2a to 2n, that are selected by the device 1, in synchronization with the clock signal generated by the clock signal generation means 21.
When the serial data transfer operation is completed, the data output terminal 11 in the synchronous serial data transfer device 1 holds the level of the last data item in the transfer data items, as shown in FIG. 14. Accordingly, since the conventional synchronous serial data transfer device 1 has the configuration described above, when the data level of an invalid data item in one of the external receiving circuits 2a to 2n is a high level (hereinafter, referred to as "H level"), it is necessary to set the level of the final data item to the H level so that the level of the output terminal 11 has the H level. Or, it is required to communicate the completion of the data transfer operation from the synchronous serial data transfer device 1 to the external receiving circuits 2a to 2n in a predetermined manner. Additionally, the electrical the connection between the synchronous serial data transfer device 1 and the external receiving circuits 2a to 2n through the data output terminal 11 and the data input terminal 13 must be broken.
Furthermore, when the external receiving circuits 2a to 2n have different levels of the invalid data items, it is necessary to change the hardware configuration of the conventional synchronous serial data transfer device 1 in order to match or to fit the external receiving circuits 2a to 2n having different levels of the invalid data items.
On the other hand, the voltage level of the clock output terminal 12 is 1 (for example, the H level) when the final data transfer operation is completed and when the clock signal is a falling enable. Further, the voltage level of the clock output terminal 12 is 0 (for example, the L level) when the final data transfer operation is completed and when the clock signal is a rising enable. Therefore, it is necessary to change the hardware configuration of the conventional synchronous serial data transfer device 1 connecting to the external receiving circuits having different clock enable edges.
The following reference is a technical example of the conventional synchronous serial data transfer device:
Japanese Laid-open Publication Number: JP-A-5/181796.
As described above in detail, because the conventional synchronous serial data transfer device 1 has the above configuration, it must be required to match or to fit the level of a final data item to be transferred to the external receiving devices according to the input receiving data invalid level of each of the external receiving circuits 2a to 2n, or it is necessary to communicate the completion of the data transfer operation to the external receiving circuits 2a to 2n in a predetermined manner so that the external receiving circuits 2a to 2n can electrically break the data transfer connections between the synchronous serial data transfer device 1 and the external receiving circuits 2a to 2n. Therefore it is necessary to change the hardware configuration of the synchronous serial data transfer device 1 when the device 1 is connected to the external receiving circuits 2a to 2n having different input receiving data invalid levels of the input data items, or when the device 1 is connected to the external receiving circuits 2a to 2n having different clock enable edges.